(a) Field of the Invention
The present invention relates to a semiconductor memory device having a reduced precharge time and, more particularly, to an improvement of a precharge circuit in the semiconductor memory device.
(b) Description of a Related Art
Some memory devices include a read circuit having a sense amplifier implemented by a current mirror circuit. FIG. 1 shows a ROM having such a read circuit. The ROM includes a sense amplifier 201 having a data line 11, a column selector (Y-selector) 202 and a memory cell array 203.
The memory cell array 203 includes a plurality of memory cells arranged in a matrix and each including a cell transistor such as MA or MB having a source connected to the ground, a drain connected to a bit line (digit line) 13, and a gate connected to a corresponding word line W1. Each memory cell MA or MB is programmed in the fabrication process thereof to have an on-state or an off-state during activation thereof depending on the data stored. The Y-selector 202 includes for each column an n-channel (n-ch) transistor such as N1 or N2 having a gate for receiving a column select signal (Y-select signal) such as Y1 or Y2, a source connected to a corresponding digit line 13, and a drain connected to the data line 11 in common with the drains of other n-ch transistors.
The sense amplifier 201 includes a precharge circuit implemented by a p-ch transistor P1 having a source connected to a source line VDD (VDD line), a gate for receiving a precharge signal and a drain connected to a node 14, and a current mirror circuit including a reference-side p-ch transistor P2 having a source connected to the source line VDD and a gate and a drain connected together to node 14 and an output-side p-ch transistor P3 having a source connected to the source line VDD and a gate connected to the gate of p-ch transistor P2 at node 14.
The sense amplifier 201 further includes an n-ch transistor N3 having a drain connected to the drain of p-ch transistor P2 at node 14, a gate connected to the output node 12 of a feed-back inverter INV1 and a source connected to the common drains of the n-ch transistors N1 and N2 of the Y-selector 202 through the data line 11, and an n-ch transistor N4 having a drain connected to the drain of p-ch transistor P3 at a node 15, a gate connected to a reference voltage line and a source connected to the ground line. The input of feed-back inverter INV1 is connected to the data line 11, and the drain of n-ch transistor N4 is connected to an output terminal OUT through an inverter INV2.
FIG. 2 shows a timing chart showing the operation of the ROM of FIG. 1. A single read cycle of the ROM includes a precharge period for precharging a selected digit line 13, and a sampling period for reading data from the selected memory cell through the digit line 13 and the data line 11.
The setting of the read cycle is such that the precharge signal falls from a high level to a low level at time t0 to effect a start of precharge period, followed by, after a time delay td, a rise of the Y-select signal from a low level to a high level. More specifically, the precharge signal is activated at the start of the precharge period, whereas the Y-select signal changes after the time delay td elapsed since the change of the precharge signal due to the delay of the Y-decoder (column decoder).
After Y-select signal Y1, for example, rises from a low level to a high level, the charge stored on the data line 11 flows to the digit line 13 to start charging of the digit line 13, which causes a fall of the potential of the data line 11.
After the potential of the digit line 11 falls below the threshold level of feed-back inverter INV1, the output node 12 of feed-back inverter INV1 rises from a low level to a high level to turn on n-ch transistor N3. Thus, the precharge current flows through p-ch transistor P1 and n-ch transistor N3, both of which are turned on at this stage, from the VDD line to the digit line 13. After the digit line 13 is charged, the node 14 connecting the drain and the gate of p-ch transistor P2 is charged up to the VDD level.
Subsequently, the precharge signal rises from the low level to a high level at time t3 to effect a data sampling period, wherein p-ch transistor P1 is turned off. If memory cell "MA" having an on-state as the stored data thereof is selected at this read cycle, the potential of node 14 falls from the VDD level to a lower level, which is lower than VDD-Vth, to turn on p-ch transistor P2 and p-ch transistor P3, wherein given Vth is the threshold voltage of p-ch transistors.
Since the transconductance (g.sub.m) of p-ch transistor P3 is set higher than the transconductance of n-ch transistor N4, the drain (node 15) of p-ch transistor P3 rises to a high level, whereby the data supplied through output terminal OUT assumes a low level.
In the conventional ROM as described above, there is a problem in that the read cycle requires a relatively long time for the precharge period especially if the ROM has a large storage capacity, i.e., if the ROM has a large number of memory cells, to thereby lower the speed of the read operation.
More specifically, a larger storage capacity of the ROM involves a larger number of memory cells connected to a digit line,. which increases the parasitic capacitance for the drains of memory cells and thus increases the load capacitance and the load resistance of the digit line, resulting in the increase of the precharge time.